IDF to Focus on 32-nm ‘Westmere’ Chips

Intel has begun producing 32-nm “Westmere” chips, the focus of the company’s Intel Developer Forum in two weeks.
Intel plans to announce on Sunday night that is has begun manufacturing its 32-nm shrink of its Core microprocessor line, which the company refers to by the umbrella code name of “Westmere”. Those chips will be spearheaded by the so-called “Dales” chips — “Clarkdale” for the desktop, and “Arrandale” for the notebook – which will contain an Intel CPU and graphics core together in the same package. Arrandale is expected to ship during the fourth quarter of 2009.
Intel is also expected to announce that its has developed a system-on-chip technology to complement its CPU efforts, leading to improved versions of its SoC efforts for the consumer, commercial, communications, and other markets. In addition, Intel plans to announce new transistor improvements.
The Intel Developer Forum will begin on Sept. 14 in San Francisco, a frequent venue for what Intel refers to as its “geekfest”. Intel plans to host 5,000 developers, technologists, and journalists, laying out its vision for 2010 and especially the all-important holiday season.
Intel tipped those holiday plans long ago, but most recently in late August at the Hot Chips conference, and with its Lynnfield launch, most likely the last major 45-nm update for the desktop PC. (Clarksfield, a 45-nm mobile chip, is expected to be announced at IDF.) Eventually, Intel will manufacture Larrabee, a chip architecture that puts both capabilities on the same die. More about Larrabee is expected at IDF.
Still, the combination of a CPU and graphics inside the main microprocessor package may put pressure on rival AMD, which has begun obliquely addressing Arrandale and Clarkdale with its Vision campaign, which addresses what a laptop equipped with a CPU can achieve. The combination should also cut power, a design feature Intel has addressed with its HUGI (Hurry Up and Get Idle”) design mantra.
Intel will also talk about a new second-generation high-k+ metal gate transistor formula, which will give Intel “a 3+ year advantage in addressing leaky and energy inefficient transistors,” according to a blog post from Intel spokesman Bill Kircos. Intel has shipped more than 200 million 45nm CPUs using high-k+ metal gate transistors, Kircos will say.
The emphasis on improved transistor manufacturing will be evidenced in the first keynote by Bob Baker, Intel’s vice president of manufacturing, who will join Intel chief executive Paul Otellini and IDF fixture Pat Gelsinger on stage on Tuesday, Sept. 14. On Wednesday, executive vice president Dadi Perlmutter will provide an update on Intel’s mobile efforts, followed by Renee James, who will update attendees on Intel’s software efforts, including the acquisition of Wind River. On Thursday, senior vice president Eric Kim and vice president Justin Rattner will update attendees on Sodaville and other system-on-chip efforts, plus more on the future of TV.

Coueresy of ExtremeTech